System C Modelling
With a rapidly approaching deadline, the client engaged Lateral Sands to design blocks for a
large SoC. The blocks were complex signal processing and data path elements, including FIR filtering, resampling, and Viterbi decoding. Deadlines meant that they could not be completed in house.
Lateral Sands provided engineers to visit the client site and discuss the
challenges in hand. We worked on specifications for blocks and then performed full design, verification and synthesis of the blocks. This was done both at the
client's site, and remotely at our design center.
The client benefited from the delivery of high quality tested modules for use in their SoC. These integrated quickly into the overall design and helped the client to achieve necessary deadlines. The use of the high quality design talent available at Lateral Sands meant the client had access to a one stop solution for their engineering needs, without the
need to recruit extra staff.
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The client engaged Laterals Sands to complete the verification test plan, testbench framework, and tests for a complex multiprocessor ASIC.
Our team performed functional verification of the instruction set operation and an exhaustive boundary condition testing of the instruction set (the customer had previously performed a major path validation). We then created a test generator in C++ to generate assembler files from a control file.
The Lateral Sands team created 1800 test files with a total of around 110,000 tests. We found 65 confirmed bugs.
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The client approached Lateral Sands to develop four models - to verify a
network multiplexor under development and for system verification. Two teams worked on the two different projects, both of which ran over 6 months.
· Project 1: Development of a SystemC model to verify a multiplexing and framing ASIC under development. Our team developed 2 SystemC models of the ASIC from the client's specification. These were interfaced to the system verification testbench. The customer provided stimulus generators and output analyzers for the testbench and our team performed testing in
Australia. A Lateral Sands engineer provided a project handover,
onsite, at the end of the project.
· Project 2: SystemC model for a framer ASIC and a model of a time and space switch. The first stage of the project involved an onsite visit to establish project parameters, technical specifications and client expectations. The team then worked remotely at our design center to generate the main functionality of the models. In the second stage, two engineers were placed on site for two weeks to integrate the models
into the system verification testbench. The team then spent another 2 months in our design center adding error correction processing to the models.
· Project 1: the client used the SystemC models to test the verification environment before the ASIC RTL was coded. Later, they were able to reuse the SystemC model for system verification
· Project 2:These models have allowed the client to conduct
architectural system level modeling for several of their ASIC designs. They have also been able to integrate the SystemC models with Verilog RTL
models to help with their verification efforts.
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The client required a complete turnkey design for three FPGAs for a radio communications project.
This project involved:
- Generating development specifications and capturing functionality to a level needed to begin hardware design.
- Meeting proposed schedules with very high quality results
- Supporting issues and modifications as needed with quick response on critical issues
- Working on site as required to generate specifications and test designs
- The utilization of industry standard development tools compatible with the client's in- house tools.
The project was completed from start to finish in our Perth Design center and met all time, quality and budget requirements. Lateral Sands provided descriptions of the design, environment and tests completed. All FPGAs were bug-free and functioned on the board first time.
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