Lateral Sands provides
complete verification solutions for ASIC, SOC and FPGA design, or we can assist
in areas such as:
- Verification Planning
- Verification environment development
- UVM/OVM/VMM expertise
- Assertion Based Verification
- DSP verification
- Metrics driven verification
- HW/SW Co-simulation
- Regression Management
Our Team
Our verification team are flexible and will work with you to develop the best possible verification strategy to suit your needs. We are proactive in anticipating and responding to changes as your specifications and designs evolve.
Our team has extensive knowledge in all areas of ASIC, SOC and FPGA verification, including
the latest methodolgies and languages,
such as UVM/OVM/VMM and SystemVerilog, SystemC, Vera, e, and C++.
|
