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Design
Verification
Modeling

Lateral Sands provides thorough and methodical verification for SOC, ASIC and FPGA design. Our verification team can provide completely independent testing of the design to give an extra level of confidence not possible with in-house verification.

Your client liaison strategy is established at the start of the engagement. This strategy allows our staff to work closely with your project team throughout the verification process. We are proactive in anticipating and responding to changes as your specifications and designs evolve.

We offer complete blackbox verification solutions or we can assist areas such as:

  • Verification Planning
  • Assertion Based Verification
  • Constrained-Random Verification
  • Object-Oriented Verification
  • Functional Coverage Techniques
  • Co-simulation
  • Environment Development and Scripting
  • Regression Management

Our Team
Our verification team are flexible and will work with you to develop the best possible verification strategy to suit your needs. Our team has extensive knowledge in all areas of SOC, ASIC, and FPGA verification, including numerous methodolgies and languages, such as Vera, e, SystemVerilog, SystemC and C++. We also have extensive experience in DSP verification for complex SOCs.